Extremely high performance at high voltage


TSMC this week announced a new manufacturing process specifically designed for High Performance Computing (HPC) products. N4X promises to combine the density of transistors and design rules of TSMC’s N5 family nodes with the ability to drive chips at very high voltages for higher frequencies, which will be especially useful for server processors and the SoCs. Interestingly, TSMC’s N4X has the potential to enable higher frequencies than even the company’s next-gen N3 process.

One of the problems caused by reducing the size of transistors is reducing the size of their contacts, which means increased contact resistance and consequent problems with power delivery. Various manufacturers use different ways to solve the contact resistance problem: Intel uses cobalt contacts instead of tungsten contacts, while other manufacturers have opted for contact formation using deposition technology. selective tungsten. While these methods work well for just about any type of chip, there are still ways to further improve power delivery for high performance computing (HPC) designs, which are relatively shameless about the total amount of power. power / voltage used. This is exactly what TSMC did to its N4X node. But before we detail the new manufacturing process, let’s see what benefits TSMC promises with it.

TSMC claims that its N4X node can allow up to 15% higher clocks compared to a similar circuit made with N5 as well as up to 4% higher frequency compared to an integrated circuit produced using its N4P node while running at 1.2V. Additionally – and apparently more importantly – the N4X can reach drive voltages above 1.2V to achieve even higher clocks. To put the numbers in context: Apple’s M1 family SoCs made at N5 operate at 3.20 GHz, but if these SoCs were produced using N4X, then using TSMC’s calculations, they could theoretically be driven to around 3.70 GHz or even higher frequency at voltages above 1.2V.

TSMC does not compare the density of the N4X’s transistors to that of other members of its N5 family, but normally processors and SoCs for HPC applications are not designed using high density libraries. As for the power supply, drive voltages above 1.2V will naturally increase power consumption compared to chips produced using other N5 class nodes, but as the node is designed for HPC / data center applications, its goal is to deliver the highest possible performance with power being a secondary concern. In fact, total power consumption has increased on HPC-class GPUs and similar parts over the past two generations now, and there is no sign that this will stop in the next two generations of products, partly thanks to the N4X.

“HPC is now TSMC’s fastest growing business segment and we are proud to introduce N4X, the first in the ‘X’ line of our extreme performance semiconductor technologies,” said Dr. Kevin Zhang, Senior Vice President of Business Development at TSMC. “The demands of the HPC segment are relentless, and TSMC has not only adapted our ‘X’ semiconductor technologies to unleash ultimate performance, but also combined it with our advanced 3DFabric packaging technologies to deliver the best platform. HPC form. “

PPA improvements announced for new process technologies
Data announced during conference calls, events, press briefings and press releases
TSMC
N5
vs
N7
N5P
vs
N5
N5HPC
vs
N5
N4
vs
N5
N4P
vs
N5
N4P
vs
N4
N4X
vs
N5
N4X
vs
N4P
N3
vs
N5
To be able to -30% -ten% ? inferior -22% ? ? -25-30%
Performance + 15% + 5% + 7% higher + 11% + 6% + 15%
Where
Following
+ 4%
or more
+ 10-15%
Logical zone

Reduction%

(Density)

0.55x

-45%

(1.8x)

0.94x

-6%

1.06x

0.94x

-6%

1.06x

?

?

0.58x

-42%

(1.7x)

Volume
Manufacturing
Q2 2020 2021 Q2 2022 2022 2023 S2 2022 H1
2024?
S1 2024? S2 2022

In order to increase performance and make control voltages greater than 1.2 V possible, TSMC had to upgrade the entire process stack.

  • First, he redesigned his FinFET transistors and optimized them for both high clocks and high drive currents, which likely means reducing resistance and stray capacitance and increasing current flow through the channel. We don’t know if he had to increase the gate-to-gate step spacing and at this point TSMC doesn’t say what it did exactly and how that affected the density of the transistors.
  • Second, it introduced new high density metal-insulator-metal (MiM) capacitors for stable power supply under extreme loads.
  • Third, he redesigned the end-of-line metal stack to deliver more power to the transistors. Again, we don’t know how this affected the density of the transistors and ultimately the size of the chips.

To a large extent, Intel has introduced similar improvements to its 10nm Enhanced SuperFin processing technology (now called Intel 7), which is not surprising as these are natural methods of increasing frequency potential.

What’s spectacular is how well TSMC has been able to increase the clock speed potential of its N5 technology over time. A 15% increase brings the N4X closer to its next-generation N3 manufacturing technology. Meanwhile, with drive voltages above 1.2V, this node will actually allow higher clocks than N3, making it especially useful for data center processors.

TSMC says it expects the first N4X designs to enter production at risk by the first half of 2023, which is a very vague description of the timeline, as that can mean very late 2022 or early 2023. Either way, it typically takes a year for a chip to go from risky production to high-volume production iteration, so it’s reasonable to expect the first N4X designs to hit the market in the near future. early 2024. This may be a weakness of N4X because by the time its N3 is fully implemented and while N4X promises to have an advantage in terms of clocks, N3 will have a major advantage in terms of density of transistors.

Source: TSMC


Source link

Previous What counts as affordable in Ypsilanti? Residents challenge the developer during the community contribution session
Next Reasons you might need to apply for a payday loan