Samsung has added a 2nm process node to its foundry roadmap, and said products built with the new technology are expected to go on sale in 2025.
Every time it lands, the chips will use gate-all-around (GAA) technology that the South Korean giant debuted in 2019. Like The register previously detailed, GAA is an attempt to pack more transistors onto silicon chips.
GAA is necessary because the current technique used to increase density – involving fin-shaped field-effect transistors (FinFETs) – relies on the fact that the structure of the transistor’s gate lifts up much like a fin. fish. This FinFET design loses its performance advantages and becomes unattractive to engineers because the devices are small, which is indeed happening as advanced manufacturing processes move towards 5nm nodes and 3 nm.
As the name suggests, the GAA moves the transistor channel upward in the gate fin so that the gate material surrounds the channel, increasing the contact area and putting the manufacturing back on track. efficient and densely packaged semiconductors. Samsung, IBM, and TSMC are all working on GAA technology.
The Korean giant calls its effort Multi-Bridge-Channel FET (MBCFET), and claims its first-generation 3nm node using the technology will deliver “up to 35% area reduction, 30% better performance, or 50% less power consumption compared to the 5 nm process. “
“The logical efficiency of three nanometers is approaching a similar level to that of the 4 nm process, which is currently in mass production,” the company said yesterday at its annual foundry forum.
Samsung previously announced that it will launch the 3nm process node in 2021. Now it says first-generation 3nm products will arrive in the first half of 2022, with a more refined version expected the following year.
The company also revealed that a 2nm process node – still based on MBCFET – “is in the early stages of development with mass production in 2025.”
Meanwhile, Samsung has also tickled its 17nm process by adding a 3D transistor architecture that it says will improve power consumption and boost performance by almost 40% compared to the company’s 28nm process. Chaebol further paid some attention to its 14nm process “to support 3.3V high voltage or flash-type onboard MRAM (eMRAM) which enables increased write speed and density.”
5G is also on Samsung’s radar, with 8nm platforms enhanced to ensure the Korean giant can deliver products suitable for mmWave RF applications.
Samsung has made massive investments in foundry capacity. Like other chipmakers, it hopes to capitalize on long-term demand for semiconductors and build supply chains that are more resilient and less dependent on inputs from China – to avoid geopolitical entanglements.
If Samsung can meet its 2025 schedule for 2nm, it will deliver it around a year after Taiwan’s TSMC plans to mass-produce its own silicon at this node. Speaking of TSMC, he hopes to deploy parts of 3nm nodes in volume in the second half of next year.
Meanwhile, IBM is putting forward its own 2nm design; However, Big Blue will need a foundry like Samsung or Intel to make this technology a reality.
And, to reiterate, the stated size of a silicon manufacturing process doesn’t really matter, as the various elements of an actual die will be larger than the name suggests. Intel recently changed the names of its manufacturing processes accordingly, to nicknames such as “Intel 3” and “20A”, in which the A stands for ångström – a unit of length equal to 0.1 nanometers. ®
One reader pointed out that the International Union of Pure and Applied Chemistry’s guestbook – the definitive compendium of chemical terminology – insists that the official contraction of ngströms is Å. The register looks forward to copying any correspondence between the union and Intel’s branding police on this matter.